USB v2.0 Soft PHY and Device Controller
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
Hi-Speed USB interfacing
Mixed-Signal Verification for USB 2.0 Physical Layer IP
Difference between USB and ULPI - Electrical Engineering Stack Exchange
Amazon.com: Waveshare USB3300 USB HS Board Host OTG Phy Low Pin ULPI MIC2075-1BM Onboard Evaluation Development Module Kit : Electronics
Synopsys IP Technical Bulletin: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
USB2 PHY | Cadence
USB3300 USB HS Board Host OTG PHY Low Pin ULPI Evaluation Development Module Kit @XYGStudy
USB3250 | Microchip Technology
TUSB1210-Q1 data sheet, product information and support | TI.com
HSIC USB 2.0 PHY IP
USB2.0 PHY – Silicon Library Inc.
The Next-Generation Interconnect | Mouser
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
PCIe/USB/SATA PHY Application Example | Renesas
USB 2.0 PHY Verification
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
USB Component: USB Device
Partitioning hi-speed USB systems - EE Times
USB3300 USB HS Board USB high-speed PHY device for ULPI interface
USB 2.0 PHY IP core | Arasan Chip Systems
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
